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What is fan-out?
When designing logic circuits, the term fan-out often comes up. Most of us probably remember that fan-out refers to the number of gates that can be hooked to the output of a logic gate and have them all function properly and reliable.  For example, when using TTL gates, you can have the output of a single AND gate tied to the inputs of approximately 10 other gates.  The AND gate is said to have a fanout of 10.
What exactly is going on with this fan-out stuff. 
Let’s stick with TTL for this example.  A TTL input looks like a resistor (Rb) tied to the base of an n-channel transistor.  For the output, there is another n-channel transistor.  The collector is tied to Vcc through another resistor (Rc). The collector is the output of the gate.  The emitters are tied to ground.
There are two cases to look at, when the output is high and when the output is low.  When an output, not connected to any other devices, is low, the transistor must sink the current through the pull-up resistor Rc.  This current is (Vcc-Vce)/Rc, where Vce is the voltage from collector to emitter in saturation.  This voltage is typically 0.2V for a silicon transistor and 0.1V for a germanium transistor.
Now consider the output is connected to another TTL input.  Since the first output is low, the transistor in the second gate will be off and the current flow out of the input of that gate will be the reverse saturation current Icbo.  Each gate that the output is connected to will contribute its Icbo to the collector current of the output transistor of the driving gate.  That means the current in the output transistor is now (Vcc-Vce)/Rc + NIcbo, where N is the number of gates connected to the output.
The second case is when the output is high.  In this case the pull-up resistor of the output transistor must source the current to turn on the input of the gate connected to the output. If there is one gate connected, the current is Ib = (Vcc-Vbe)/(Rc +Rb), where Vbe is the base-emitter voltage of the input gate, Rc is the pull-up resistor in the output gate and Rb is the input resistor connected to the base of the input transistor. For each additional gate connected to the output there will be an additional current required to drive the base of the input transistor.  All of these currents will flow through Rc, which will lower the value of Vce.  Eventually there will not be enough voltage to provide the current needed to turn on the input transistors and the connection will become unreliable. 

AC vs. DC fan-out
So far, we have been discussing DC fan-out.  In a real system, you must consider the fact that input gates have capacitance.  The capacitance and the resistances form low pass filters. That is, they slow things down.  So, in addition to power supply concerns, the designer must consider propagation delays.  This sets a speed limit on the system.
What’s a poor designer to do?
The CMOS family has the advantage that it has a high DC resistance.  That means that DC fanout is not such a big problem for that family of logic circuits.  Unfortunately, the input capacitance is high, which causes propagation delay.  That is why despite the advantages of CMOS, TTL has endured so long.
As with everything an engineer does, fan-out is a tradeoff.  In this case between speed and current sourcing ability.  If speed is the main factor you might want to use TTL.  If you are also faced with large fan-out concerns, you can use a buffer.  While most TTL gates have a fanout of 10, buffers might have a fanout 3 times that amount.  On the other had if you are not pushing the limits of speed, and power is your primary concern, i.e. battery life, then CMOS is your best choice.

Final thoughts
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