The Celtic Engineer is a weekly newsletter produced by Celtic Engineering Solutions.  We hope you enjoy it.  If you have any suggestions for topics, would like to give feedback or want your email added to the distribution list please send an email to [email protected].

Yet another Serial Bus

SPI Bus (sometimes pronounced ‘spy’ bus) is short for Serial Peripheral Interface bus.  It is a 4-wire communication protocol, not counting power and ground.  This protocol was designed by the Motorola Corporation in the late 1980’s.  Using SPI, you communicate in both directions at the same time, full-duplex mode.  The arrangement is master-slave.  There can only be a single master but multiple slave devices are possible.

What’s the setup?

There are three common lines; MOSI, MISO and SCLK.  MOSI is short for Master Out, Slave In.  This is the data being sent from the master out to peripherals attached to the bus.  The response comes back on the MISO line; Master In, Slave Out.  The data is transferred synchronously using a clock, SCLK that is controlled by the master device.
There might be a single slave device or there might be many devices connected to the SPI bus.  To indicate which slave device is being talked to, the use of a SS, Slave Select, line or Chip select line is used.  Each peripheral must have a unique select line.  In microcontrollers that have a SPI peripheral where you set up the communication protocol ahead of time, you need to remember that the unique select line is not controlled by the peripheral, but must be selected (usually active low) before sending data to the SPI peripheral for transfer.
This might not be music, but there are still modes
In music theory, a mode is a scale of musical notes.  When talking about a SPI Bus, mode referees to the resting state of the clock line and the phase where data is read.  The clock can be normally in a low state and transition up and then back down for a clock pulse or it can be normally high and pulse low and then back high for a clock pulse.
For each clock pulse, there are two clock edges a falling edge (high to low transition) and a raising edge.  You can grab data on either edge as long as both the master and the slave agree on which edge that will be.  There are said to be four modes in SPI.  The clock can be either high or low (during resting) and you can collect data on the rising or falling edge.

All Aboard! 

When the master initiates a transfer, it is responsible for selecting the slave device, running the clock and sending the data.  The data could be a request for information.  For example, if the master wanted to know the chip ID for a particular device it might send an 8-bit character 0x0D (see the datasheet for the particular slave device).  When this particular peripheral receives 0x0D it responds by sending its ID, say 0x15.  The particular numbers are not important for this example.  Most SPI buses are 8-bit, but there are some that are 12 or 16 bits as well.
The master will select the slave device by lowering its chip select line. Then it will start toggling the clock and sending out data one bit at a time.  At the same time, the data is clocked out, data is clocked in. After 8 bits are transferred, the peripheral chip will have received the ID request and it is ready to respond.  But what about the 8 bits that were transferred to the master?  Those are garbage.  They are most likely all zero’s or all 1’s as the peripheral should not have actively been transferring anything yet.
Next the master must send out 8 more clocks to get the data ID back.  It really does not matter what the data that the master sends at this point, because we are awaiting a response.  Clock out eight 0’s or eight 1’s.  At the end, the ID response should be in the receiving buffer.

What do you mean you’re not ready?

In the above example, we sent out the ID request and then immediately began receiving the ID.  In reality, there may be a wait time between when the request is send and when the slave is ready to send the data.  This information will be in the datasheet.  Many times, the wait time is so much less than a SPI clock cycle that you can continue without pausing.  Other time, you must observe a proper wait time.
On some peripherals, there is an extra line to deal with this situation. It is an interrupt line sent from the slave to the master indicating that some event has happened.  It could mean that the data you requested is ready.  Or it could also mean that some event has happened such as an acceleration above a threshold.

How to transfer larger amounts of data

Even though only eight bits are transferred at a time, an arbitrary amount of data can be transferred but setting up the proper protocol ahead of time.  You might have a block transfer that always transfers 200 bytes, or you might have a variable amount where you say essentially “I am going to send you a bunch of data, and the amount will be 200 bytes.”  That would require a two-byte transfer to initiate the transfer then the data.  This will all be in the datasheet, unless you are transferring from one MCU to another.  In that case you will be writing your own datasheet and must set up the exchange protocol.

To be or not to be

The advantages of SPI include: faster transfer rate than I2C or SMBus, arbitrary message size, no address, no arbitration, low power requirements and simple firmware implementation. The disadvantages include: requires more pins, no handshaking (is anyone listening?), no error checking, many variations and only good over short distances.

Final thoughts

This newsletter is sponsored by Celtic Engineering Solutions LLC, a design engineering firm based out of West Jordan, Utah, which can be found on the web at:  You can find the newsletter on the company blog, LinkedIn or by subscribing.  Send your emails to The Celtic Engineer at:  [email protected].